Slides
15th International Workshop on
Constructive Side-Channel Analysis and Secure Design
Cosade 2024
Constructive Side-Channel Analysis and Secure Design
Cosade 2024
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Patrick Karl, Jonas Schupp and Georg Sigl. The Impact of Hash Primitives and Communication Overhead for Hardware-Accelerated SPHINCS+
Dilara Toprakhisar, Svetla Nikova and Ventzislav Nikov. CAPABARA: A Combined Attack on CAPA
Oussama Sayari, Soundes Marzougui, Thomas Aulbach, Juliane Krämer and Jean-Pierre Seifert. HaMAYO: A Fault-Tolerant Reconfigurable Hardware Implementation of the MAYO Signature Scheme
Amélie Marotta, Ronan Lashermes, Guillaume Bouffard, Olivier Sentieys and Rachid Dafali. Characterizing and Modeling Synchronous Clock-Glitch Fault Injection
Niklas Stein and Michael Pehl. Leakage Sources of the ICLooPUF: Analysis of a Side-Channel Protected Oscillator-Based PUF
Thomas Marquet and Elisabeth Oswald. Exploring Multi-Task Learning in the Context of Masked AES Implementations
Nicolas Belleville and Loïc Masure. Hiding Behind the One that I Hide -- Combining Loop Shuffling and Code Polymorphism for Enhanced AES Side-Channel Security
Javad Bahrami, Mohammad Ebrahimabadi, Sylvain Guilley, Jean-Luc Danger and Naghmeh Karimi. Impact of Process Mismatch and Device Aging on SR-Latch Based True Random Number Generators
Barış Ege, Bob Swinkels, Dilara Toprakhisar and Praveen Vadnala. Practical Improvements to Statistical Ineffective Fault Attacks
Fabrizio De Santis, Shibam Mukherjee, Christian Rechberger, Stjepan Picek, Fabian Schmid and Marc Stöttinger. Towards Private Deep Learning-based Side-channel Analysis using Homomorphic Encryption
Ioana Savu, Marina Krček, Guilherme Perin, Lichao Wu and Stjepan Picek. The Need for MORE: Unsupervised Side-channel Analysis with Single Network Training and Multi-output Regression
Mustafa Khairallah, Srinivasan Yadhunathan and Shivam Bhasin. Lightweight Leakage-Resilient PRNG from TBCs using Superposition
Arpan Jati, Naina Gupta, Anupam Chattopadhyay and Somitra Sanadhya. EFFLUX-F2: A high performance hardware security evaluation board
Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki and Makoto Nagata. On-chip evaluation of voltage drops and fault occurrence induced by Si backside EM injection
Keynote 1 - Gaëtan Cassiers, Composable masking schemes